The present invention concerns a method for cascading detachable conditional access modules. It also concerns a circuit for inserting a predetermined sequence as described in the method and a circuit for detecting such sequence.
In the field of digital pay television, the decoders currently on the market include, as depicted schematically in FIG. 1, an input circuit 1 or xe2x80x9cfront endxe2x80x9d consisting amongst other things of a demodulator, a demultiplexer 2 associated with a descrambler 3, a microprocessor 4 connected to the descrambler 3 in order notably to supply the control word CW, and video 5 and audio 6 circuits connected at the output of the demultiplexer. A chip card 7 including notably data authorising access to the programmes is connected in a known manner to the microprocessor 4 of the decoder. The decoder receives at its input a xe2x80x9cmultiplexxe2x80x9d signal which can contain a very large number of programmes, some being in clear, others being scrambled. The video signal is sent over the input circuit 1, which makes it possible to recover at the output a data stream TS or xe2x80x9ctransport streamxe2x80x9d consisting of packets of fixed length separated by an interpacket space of fixed length, each packet being detected by a packet clock PC. The role of the demultiplexer, descrambler, microprocessor and chip card, is notably, to descramble the scrambled packets belonging to the programme selected in respect of which the user has right of access. Currently the service providers desiring to transmit scrambled programmes define the specificities of their own decoder, and in particular those of their access control system. These specific elements or secrets of the conditional access sub-system prevent its standardisation.
In order to remedy these drawbacks and to allow the production of future standard digital television reception systems, it has been proposed to isolate the conditional access sub-system within a detachable module in the chip card format or PCMCIA format. In this case, several detachable modules can be connected to a single decoder. The entire data flow is obtained at the output of the input circuit of the decoder and passes successively through each module connected in cascade. Each module makes it possible to descramble the scrambled packets which concern it. Thus, when the conditional access information used for the selected programme is recognised by the module and when the user has right of access to this programme, then and only in such cases are the corresponding packets of the data flow descrambled whilst keeping their relative positions. A decoder of the above type is depicted schematically in FIG. 2. The decoder includes an input circuit 1xe2x80x2 which receives the high-frequency signal S, demodulates it so as to obtain the data stream TS0 or xe2x80x9ctransport streamxe2x80x9d and the packet clock PCL, and then sends it to the input of the first detachable module A. Each detachable module also includes a demultiplexer 2xe2x80x2 associated with a descrambler 3xe2x80x2 and a microprocessor 4xe2x80x2. It can be in the chip card format or in the format of a PCMCIA module such as the ones existing in the microcomputing world. The data stream TS1, possible partly descrambled by the above circuits, leaves the module offset in time with respect to the stream through a dedicated output, as depicted on the interface 5xe2x80x2. It is then sent to a dedicated input of the second detachable module B, where it undergoes identical processing and so on according to the number of detachable modules which may be connected to the decoder. The data stream TS2 output from the last module is sent to the input of a demultiplexer 6xe2x80x2 in the decoder which is connected in a known manner to the audio 8xe2x80x2 and video 7xe2x80x2 circuits. In addition, the decoder includes a microprocessor 9xe2x80x2 connected to each microprocessor 4xe2x80x2 situated in each detachable module and to the demultiplexer 6xe2x80x2. As mentioned above, the data stream at the output of a module is offset in time with respect to the data stream at the input, and it is therefore necessary to have a clock enabling the data to be found, as in the case of decoders currently used. Moreover, the data stream is divided into bit packets of fixed length separated from each other by a space of fixed length. In this case, a packet clock PC0 is associated with the data stream in order to indicate the start and end of a packet. This packet clock is in general used at the detachable module. Thus, in Europe, the proposed common interface provides for an incoming packet clock PC0-PC1 and an outgoing packet clock PC1-PC2, which requires two dedicated interface pins, as depicted in FIG. 2, which corresponds to the DVB proposals in the course of standardisation. In the USA, the proposed detachable module provides for a packet clock at the input of the module, but no packet clock at the output. Though this proposal makes it possible to save on an interface pin, it has the drawback that the detachable module must be able to provide, at the decoder and possibly at the other modules, information about the delay given to the packets of the data stream passing through it so that the decoder and the detachable modules are able to reconstruct the packet clock of the re-entering data stream through a correct offset of the reference packet clock.
The aim of the present invention is to remedy the above drawbacks by proposing a method which makes it possible not to use dedicated pins at the module/decoder interface, in order to obtain the packet clock in each module and in the decoder.
The object of the present invention is a method for cascading detachable conditional access modules without having recourse to a packet clock signal, each module having pass through it a data stream formed by packets of fixed length separated by a space of fixed length, characterised in that the interpacket space is filled with a predetermined sequence which does not interfere with the useful content of the packets, this sequence being used to regenerate a packet clock.
According to a preferential embodiment, the predetermined sequence consists of an increasing or decreasing series of binary data. Preferably the predetermined sequence is continued by a data item of determined and identical value located at the start of all the packets.
Another object of the present invention is a circuit for inserting the predetermined sequence located at the output of the input circuit of the decoder. The circuit includes a multiplex receiving the original data stream at a first input and, at a second input, the data in the predetermined sequence coming from a means generating the predetermined sequence, a start of packet and end of packet detector enabling either the first input or the second input to be selected.
Yet another object of the present invention is a circuit for detecting the predetermined sequence located at the modules and decoder. This circuit includes:
a comparator receiving at a first input the data stream incorporating the predetermined sequence between each packet and at a second input the data of the predetermined sequence;
a means for generating the data of the predetermined sequence, this means being addressed by the output of the comparator so as to send the first data item of the predetermined sequence when the comparator detects inequality and to send the following data item of the predetermined sequence when the comparator detects equality, and
a means generating a pulse corresponding to the length of a packet, this said means being activated by the detection of the last data item of the predetermined sequence.